In recent years, there have been demands for high-value added, highly-functional, small and light mobile products typified by cellular phone devices with cameras, built-in TVs, or the like. Thus, there have been strong requests for the miniaturization and high-density mounting of components of the mobile products and the high functionality of circuit substrates. In these circumstances, in order to realize high-density mounting, attention has been shifted from two-dimensional mounting by which components are arranged in a plane to three-dimensional mounting by which components are three-dimensionally stacked. The three-dimensional mounting is performed with a 3D package (for example, a stack CSP) in which bare chips are stacked or a package stacked 3D device obtained by forming a semiconductor chip into a stand-alone temporary package and three-dimensionally stacking a plurality of the temporary packages. Moreover, techniques are available which arrange wiring substrates in multiple layers on each of which electronic components (a semiconductor chip, a passive component, and the like) are mounted, thereby realizing high-density/sophisticated mounting. For example, in a structure related to the above-described techniques and disclosed in Patent Document 1, wiring substrates are connected together via inner via holes in order to electrically connect the substrates together. The structure allows the substrates to be wired together with a minimum electric wiring length and is thus useful for applications requiring excellent high-frequency characteristics. However, the structure can only be inspected with the substrates stacked. Thus, even if a defect is found in the structure after completion, the built-in wiring and components disadvantageously prevent the defect from being analyzed or corrected.
Furthermore, some electronic components, for example, memories, involve a short supply cycle. Thus, if such electronic components are disposed of or packages thereof are changed, the circuits need to be drastically changed. This is disadvantageous in terms of time required for design and development. For example, in structures disclosed in Patent Documents 2 to 5, electrodes between which wiring and connections are made on the surface of or in the inner layer of a substrate are placed around the periphery of the substrate. Thus, substrates are electrically connected together by connecting, for example, a conductor such as a lead frame to the peripheral electrodes or connecting the electrodes together via connectors. However, with these methods, since the electrodes are located at the end face of each of the substrates, the number of electrodes connecting the substrates together is limited by the sizes or shapes of the substrates. Furthermore, the electric wiring needs to be long enough to reach the end face of the substrate. Thus, the structures are disadvantageously unsuitable for applications requiring excellent high-frequency characteristics. In contrast, with these methods, the substrates can be individually inspected, of which the substrates determined to be acceptable can be arranged in multiple layers advantageously. Furthermore, even if a defect occurs in the substrate, the electrodes at the substrate end face enable electrical analysis and correction of the defect and repair of the defective component. Moreover, even if any component is disposed of, only the substrate including the waste component needs to be modified. This also contributes to development efficiency.    Patent Document 1: Japanese Patent Laid-Open No. 11-220262    Patent Document 2: Japanese Patent Laid-Open No. 1-226192    Patent Document 3: Japanese Patent Laid-Open No. 4-262376    Patent Document 4: Japanese Patent Laid-Open No. 4-345083    Patent Document 5: Japanese Patent Laid-Open No. 2005-217348